The present invention relates to a differential amplifier and a data driver and, more particularly, to a differential amplifier having an interpolation function for outputting an intermediate voltage between two input voltages and a data driver having plural such differential amplifiers.
In recent years, many thin display devices such as liquid crystal display devices and organic light emitting diode (OLED) display devices have been introduced in the market. An active-matrix driving method is among the driving methods used for such display devices. Generally, a thin display device using an active-matrix driving method includes a display panel which has scanning lines and data lines arranged in a grid pattern with a pixel having a pixel switch (thin-film transistor) and a display element section provided at each of the scanning line and data line intersections, a gate driver which outputs a scanning signal for turning on/off the pixel switch of each pixel to each scanning line, and a data driver which outputs a gradation voltage signal corresponding to video data to each data line. In such a display device, when the pixel switches are turned on by scanning signals, the gradation voltage signals inputted to the respective data lines are applied to the display element sections causing the display element sections to change their brightness according to the gradation voltage signals so as to realize image display on the display device.
In a liquid crystal display device, a display panel includes two substrates with liquid crystals sealed therebetween and, in the display element section of each pixel, the liquid crystal transmittance is controlled according to a gradation voltage signal received via the pixel switch so as to change display brightness. A backlight is provided as a light source behind the display panel. In an OLED (Organic Light Emitting Diode) display device, a display panel includes pixels each provided with an OLED as a display element and a current control element (thin-film transistor) for controlling the drive current for the OLED. In the display element section of each pixel, the drive current for driving the OLED is controlled according to the gradation voltage signal applied via the pixel switch causing the OLED to emit light according to the drive current so as to change the brightness of the OLED. Even though there are OLED display devices in which the drive currents for OLEDs are supplied directly to the data lines, the present invention is limited to a configuration in which gradation voltage signals are supplied to the data lines.
In the above display device, one screen portion of data is rewritten in one frame period (normally, about 0.017 second based on 60-Hz driving). The scanning lines select the pixel lines sequentially one by one (by turning the pixel switches along the pixel line on). During the period of time a pixel line is selected, the display element section of each pixel along the selected pixel line is provided with a gradation voltage signal from the corresponding data line via the corresponding pixel switch. The period of time during which a pixel line is selected approximately equals one frame period divided by the number of scanning lines. Every time a pixel line is selected, the data driver outputs gradation voltage signals corresponding to video data to the respective data lines. In the following, a data driver for driving an active matrix display device and differential amplifiers used in the output circuit of a data driver will be described.
The data driver generates reference voltages corresponding to gradation characteristics by dividing, using resistors, a γ voltage applied from outside and selects, using a D/A converter, a reference voltage corresponding to digital input video data. The selected reference voltage is inputted to a differential amplifier (hereinafter also referred to as an “output amplifier”) of a voltage follower. The data driver is provided with plural D/A converters and differential amplifiers (output amplifiers) corresponding to the number of data lines of the display panel and outputs a gradation voltage signal corresponding to video data to each data line of the display panel.
In recent years, display devices for TVs and personal computers have been growing larger in screen size and higher in definition. As a result, the load capacity of data lines of each display device has increased requiring the data driver to be capable of driving larger loads (data lines) at higher speed. As for color display, the number of colors (gradation levels) has been increasing promoting transition from 260,000-color display using 6-bit, RGB digital video data to 8-bit, 16,700,000-color display and further to 10-bit, 1,000,000,000-color display.
The increases in the number of bits per color for each pixel cause the number of gradation voltage levels outputted from a data driver to increase correspondingly, namely, from 64 gradation levels for 6 bits/color to 256 gradation levels for 8 bits/color and further to 1024 gradation levels for 10 bits/color. When the number of gradation levels increases, the minimum value between gradation voltages decreases. Hence, the output amplifiers to be used are required to offer improved output voltage accuracy and meet severer characteristic specifications, for example, concerning output deviations.
A data driver compatible with video data using an increased number of bits per color includes larger D/A converter circuits (including more elements) used to select a reference voltage for each pixel out of plural reference voltages corresponding to the number of gradation levels. This is a factor in increasing the chip area of each data driver LSI. Using an amplifier having an interpolation function (hereinafter also referred to as an “interpolating amplifier”) as means of suppressing expansion of the scale of D/A converter circuits is disclosed in Japanese Patent Laid-Open No. 2006-050296.
FIG. 9 is a block diagram of a data driver 100 disclosed in Japanese Patent Laid-Open No. 2006-050296. As shown in FIG. 9, the data driver 100 includes a latch address selector 181, a latch 182, a reference voltage generation circuit 186, decoders (for example, D/A converters) 187, and output amplifiers 188. In the data driver 100, the output amplifiers 188 are interpolating amplifiers. Each output amplifier 188 interpolates input voltages Vin1 and Vin2 at a ratio of 1:1. Namely, when input voltages Vin1 and Vin2 are equal, the output amplifier 188 outputs input voltage Vin1 (or input voltage Vin2) as output voltage Vout. When input voltages Vin1 and Vin2 are not equal, the output amplifier 188 outputs an intermediate voltage between the input voltages Vin1 and Vin2 as an output voltage. With the output amplifier having an interpolating function provided, the decoder 187 can have a configuration in which, out of reference voltages (V0, V2, V4, . . . , V2n) corresponding to every second gradation voltage, two same reference voltages or two adjacent reference voltages are selected according to video data. Since this can approximately halve the number of reference voltages selected by the decoder 187, the circuit scale (number of elements) of the decoder 187 can be reduced.
FIG. 10 shows a circuit diagram of the output amplifier 188 having an interpolating function. The basic configuration of the output amplifier 188 shown in FIG. 10 is based on a configuration disclosed in Japanese Patent Laid-Open No. Hei 06 (1994)-326529 (i.e. configuration shown in FIG. 1 of Japanese Patent Laid-Open No. Hei 06 (1994)-326529 applied to a feedback amplifier). The output amplifier 188 has a differential input section 210 and an output amplification section 211. The differential input section 210 has two n-channel differential pairs each including NMOS transistors and two p-channel differential pairs each including PMOS transistors. The output amplification section 211 has low-voltage cascode current mirrors 250 and 280, connection stages (floating current sources) 260 and 270, and output transistors 291 and 292.
The low-voltage cascode current mirror 250 includes PMOS transistors 251 to 254 and receives the differential current outputs of the two n-channel differential pairs having commonly coupled output pairs. The low-voltage cascode current mirror 280 includes NMOS transistors 281 to 284 and receives the differential current outputs of the two p-channel differential pairs having commonly coupled output pairs. The connection stage 260 couples the output of the low-voltage cascode current mirror 250 (drain of the PMOS transistor 254) and the output of the low-voltage cascode current mirror 280 (drain of the NMOS transistor 284). The connection stage 270 couples the input to the low-voltage cascode current mirror 250 (drain of the PMOS transistor 253) and the input to the low-voltage cascode current mirror 280 (drain of the NMOS transistor 283). The output transistor 291 is a PMOS transistor whose drain is coupled to an output terminal, whose gate is coupled to a coupling node between the output of the low-voltage cascode current mirror 250 and the connection stage 260, and whose source is coupled to power supply VDD on the high potential side. The output transistor 292 is an NMOS transistor whose drain is coupled to the output terminal, whose gate is coupled to a coupling node between the output of the low-voltage cascode current mirror 280 and the connection stage 260, and whose source is coupled to power supply VSS on the low potential side. The output amplifier 188 with its differential input section 210 having n-channel differential pairs and p-channel differential pairs makes up a rail-to-rail amplifier and the voltages inputted thereto are close to the supply voltages. In cases where either the n-channel differential pairs or the p-channel differential pairs stop operating, the other differential pairs operate enabling output amplification to be continued in a voltage range identical to the supply voltage range.
The differential input section 210 of the output amplifier 188 shown in FIG. 10 includes two n-channel differential pairs ((221, 2221 and (223, 224)) and two p-channel differential pairs ((225, 226) and (227, 228)). The four differential pairs are driven by as many current sources (231, 232, 233, and 234), respectively. The first n-channel differential pair (221, 222) and the first p-channel differential pair (225, 226) have input voltage Vin1 inputted to their first input terminals (gates of the transistors 221 and 225), respectively, out of their input pairs and have output voltage Vout inputted to their second input terminals (gates of the transistors 222 and 226), respectively, out of their input pairs. The second n-channel differential pair (223, 224) and the second p-channel differential pair (227, 228) have input voltage Vin2 inputted to their first input terminals (gates of the transistors 223 and 227), respectively, out of their input pairs and have output voltage Vout inputted to their second input terminals (gates of the transistors 224 and 228), respectively, out of their input pairs. The output pairs of the n-channel differential pairs (221, 222) and (223, 224) are commonly coupled. One, N201, of the output pair nodes is coupled to the output side node (coupling node between the PMOS transistors 252 and 254) of the current mirror 250. The other, N202, of the output pair nodes is coupled to the input side node (coupling node between the PMOS transistors 251 and 253) of the current mirror 250. The output pairs of the p-channel differential pairs (225, 226) and (227, 228) are also commonly coupled. One, N203, of the output pair nodes is coupled to the output side node (coupling node between the NMOS transistors 282 and 284) of the current mirror 280. The other, N204, of the output pair nodes is coupled to the input side node (coupling node between the NMOS transistors 281 and 283) of the current mirror 280.
Now, description will be focused on the n-channel differential pairs (221, 222) and (223, 224). When it is assumed that the transistors making up the n-channel differential pairs are equally sized, the drain currents I (221), I (222), I (223), and I (224) are given by the following equations.I(221)=(β/2)(Vin1−Vs1−VTH))^2  (1)I(222)=(β/2)(Vout−Vs1−VTH))^2  (2)I(223)=(β/2)(Vin2−Vs2−VTH))^2  (3)I(224)=(β/2)(Vout−Vs2−VTH))^2  (4)where β is a gain factor given by (β=μ(W/L)(∈x/tox) where μ is the effective mobility of electrons, ∈x is the dielectric constant of the gate insulating film, tox is the film thickness of the gate insulating film, W is the channel width, and L is the channel length), VTH is a threshold voltage, and Vs1 and Vs2 are the common source voltages of the differential pairs (221, 222) and (223 and 224), respectively.
The output current (I (221)+I (223)) of one, N201, of the common output pair nodes of the n-channel differential pairs (221, 222) and (223, 224) is coupled to the output current of the current mirror 250 via the output side node (coupling node between the PMOS transistors 252 and 254) of the current mirror 250. The output current (I (222)+I (224)) of the other, N202, of the common output pair nodes of the n-channel differential pairs (221, 222) and (223, 224) is coupled to the input current to the current mirror 250 via the input side node (coupling node between the PMOS transistors 251 and 253) of the current mirror 250. The output amplifier 188 controls the output voltage Vout so as to equalize the input current to and the output current from current mirror 250. Namely, the drain currents I (221) to I (224) are related as expressed as follows.I(221)+I(223)=I(222)+I(224)  (5)
The output currents of the current sources 231 and 232 for driving the n-channel differential pairs (221, 222) and (223, 224) are equalized. This causes the drain currents I (221) to I (224) to be related as follows.I(221)+I(222)=I(223)+I(224)  (6)
Then, equations (7) and (8) are obtained from equations (5) and (6).I(221)=I(224)  (7)I(222)=I(223)  (8)
Assigning equations (1) to (4) into equations (7) and (8) thereby eliminating Vs1 and Vs2 generates equation (9).Vout=(Vin1+Vin2)/2  (9)
By making similar calculations also for the p-channel differential pairs (225, 226) and (227, 228), an equation similar to equation (9) can be obtained. Namely, the output amplifier 188 shown in FIG. 10 can, by being provided with the two input voltages Vin1 and Vin2, output an intermediate voltage between the two input voltages (interpolated voltage). This input/output voltage characteristic of an interpolating amplifier is also disclosed in, for example, Japanese Patent Laid-Open No. 2000-183747.
For the data driver 100, an expansion of the circuit scale of decoders (for example, D/A converters) for processing multi-bit video data can be suppressed by using the output amplifier 188 shown in FIG. 10. It is, however, pointed out in Japanese Patent Laid-Open No. 2006-050296 that the output voltage error enlarges in certain voltage ranges near either of the supply voltages. The graph shown in FIG. 11 is used in Japanese Patent Laid-Open No. 2006-050296 in describing the above problem. The graph shown in FIG. 11 shows steady-state characteristics of output voltage setting (expected output voltage) versus output voltage error with the two input voltages Vin1 and Vin2 (Vin1>Vin2) of the output amplifier 188 differing from each other by 0.2 V. Referring to FIG. 11, in an expected output voltage range of about 0.5 V to 2V on the low potential supply voltage side, the output voltage error enlarges in the positive direction and, in an expected output voltage range of about 13 V to 14.5 V on the high potential supply voltage side, the output voltage error enlarges in the negative direction. Such an increase in output voltage error occurring when the expected output voltage is near a supply voltage is caused, for example, in cases where the two input voltages Vin1 and Vin2 lower when the expected output voltage is near the supply voltage on the low potential side causing the n-channel differential pairs provided with the low-potential input voltage Vin2 to stop first and the n-channel differential pairs provided with the high potential input voltage Vin1 to stop next. What causes the increase in output voltage error is breakdown of the relationship, expressed by the above equations (1) to (8), between the n-channel differential pairs. The relationship breakdown results when, in the process leading to stopping of the n-channel differential pairs, the gate-source voltage in each transistor included in each differential pair lowers to decrease the drain-to-source current. Note that, when the two n-channel differential pairs both stop, only the two p-channel differential pairs function. This decreases the output voltage error and puts the output voltage into a normal state. When the two input voltages Vin1 and Vin2 rise with the expected output voltage being near the supply voltage on the high potential side, causing the p-channel differential pair provided with the high-potential input voltage Vin1 to stop first and the p-channel differential pair provided with the low-potential input voltage Vin2 to stop next, the output voltage error increases.
The output voltage error occurring when the expected output voltage is near a supply voltage increases more when the difference between the input voltages Vin1 and Vin2 is larger. Thus, an interpolating amplifier like the one shown in FIG. 10 has a problem that, in an expected output voltage range near a supply voltage where the output voltage error increases, the interpolating amplifier cannot provide an output voltage with high accuracy.
The mechanism by which, according to analysis made by the inventors of the present invention, the output voltage error of the output amplifier 188 shown in FIG. 10 increases will be described below. FIG. 12 shows graphs representing steady-state characteristics of output voltage setting (expected output voltage) versus output voltage error prepared for use in explaining the mechanism by which the output voltage error of the output amplifier 188 shown in FIG. 10 increases. The operation example shown in FIG. 12 is based on the settings of the output amplifier 188 in which the input voltage Vin1 is higher by ΔV than the input voltage Vin2 (Vin1−Vin2=ΔV where ΔV>0) and in which the output voltage setting equals an intermediate voltage between the input voltages Vin1 and Vin2 ((Vin1+Vin2)/2).
When, in the interpolating amplifier shown in FIG. 10, interpolation is normally performed, the n-channel differential pairs (221, 222) and (223, 224) are related as expressed by, the above equations (7) and (8). When the input voltage Vin1 is higher than the input voltage Vin2, the currents I (221) and I (224) are larger than the currents I (222) and I (223). In the present operation example, the currents I (221) to I (224) are related as follows: I (221)=I (224)=In2; and I (222)=I (223)=In1; where In2>In1. The total current (In1+In2) corresponds to the current values outputted from the current sources 231 and 232 (outputting equal currents). The p-channel differential pairs (225, 226) and (227, 228) are similarly related. Namely, when interpolation is normally performed with the input voltage Vin1 being higher than the input voltage Vin2, the currents I (227) and I (226) are larger than the currents I (225) and I (228), and the currents I (225) to I (228) are related as follows: I (227)=I (226)=Ip2; and I (225)=I (228)=Ip1; where Ip2>Ip1. The total current (Ip1+Ip2) corresponds to the current values outputted from the current sources 233 and 234 (outputting equal currents). The current values in the p-channel differential pairs are represented by absolute values of their drain-to-source currents.
In FIG. 12, part (1) represents the current characteristics of transistors 111 to 114 included in the n-channel differential pairs (221, 222) and (223, 224). In part (1), currents I (221) and I (222) are represented by solid lines and currents I (223) and I (224) are represented by broken lines. When the output voltage setting is in a range near the high potential supply voltage VDD, the currents flowing through the transistors included in the n-channel differential pairs are kept constant, namely, I (221)=I (224)=In2 and I (222)=I (223)=In1. In this state, interpolation is performed normally. When, with the output Voltage setting being in a range near the low potential supply voltage VSS, the input voltages Vin1 and Vin2 lower causing the output voltage setting to reach Vd, first the common source terminal of the n-channel differential pair (223, 224) provided with the low potential input voltage Vin2 reaches the low potential supply voltage VSS. When the output voltage setting further lowers, with the common source terminal voltage of the n-channel differential pair (223, 224) being unable to drop below the low potential supply voltage VSS, only the input voltage for the differential pair (223, 224) lowers (i.e. gate-source voltages of the transistors 223 and 224 lower). Subsequently, as the output voltage setting drops below Vd, the currents I (223) and I (224) start decreasing. When the output voltage setting drops to voltage Vb, the currents I (223) and I (224) become almost zero causing the n-channel differential pair (223, 224) to stop. In the n-channel differential pair (221, 222) provided with the input voltage Vin1, on the other hand, the common source terminal voltage reaches the low potential supply voltage VSS when the output voltage setting drops to voltage Vc. When the output voltage setting further drops, only the input voltage for the n-channel differential pair (221, 222) lowers (gate-source voltages of the transistors 221 and 222 decrease). Subsequently, as the output voltage setting drops below Vc, the currents I (221) and I (222) start decreasing. When the output voltage setting drops to Va, the currents I (221) and I (222) become almost zero causing the n-channel differential pair (221, 222) to stop. The potential differences between the voltages Va and Vb and between the voltages Vc and Vd depend on ΔV, and the magnitude relationship between the voltages Vb and Vc varies depending on ΔV and the transistor characteristics of the n-channel differential pairs. In the operation example shown in FIG. 12, Vb<Vc.
In FIG. 12, part (2) represents the characteristic (characteristic curve Isn_ref) of the output current difference between the nodes N201 and N202 (I (N201)−I (N202)) of the differential input section 210. The output current I (N201) is the sum of the currents I (221) and I (223) of the n-channel differential pairs, and the output current I (N202) is the sum of the currents I (222) and I (224) of the n-channel differential pairs. The output currents I (N201) and I (N202) are coupled to the currents at the output side node and input side node, respectively, of the current mirror 250 in the output amplification section 211. According to the steady-state characteristics with interpolation being performed normally, the output current difference (I (N201)−I (N202)) is normally zero. In part (2) of FIG. 12, whereas the output current difference (I (N201)−I (N202)) is zero when the output voltage setting is in a range near the high potential supply voltage VDD, the output current difference increases in the positive direction when the output voltage setting is in the range of Vd to Va to be near the low potential supply voltage VSS. The increase in the output current difference (I (N201)−I (N202)) depends on current changes in the n-channel differential pairs. To be concrete, referring to part (1) of FIG. 12, when the output voltage setting drops below voltage Vd, the currents I (223) and I (224) decrease, respectively. At this time, the current I (224) decreases more than the current I (223), whereas the currents I (221) and I (222) do not change. Namely, the output current I (N202) decreases more than the output current I (N201), causing the output current difference (I (N201)−I (N202)) to increase in the positive direction. When the output voltage setting drops below voltage Vc, in addition to the currents I (223) and I (224), the currents I (221) and I (222) also start decreasing. At this time, the current I (221) decreases more than the current I (222). Namely, the output current difference (I (N201)−I (N202)), depending on changes in the currents I (221), I (222), I (223) and I (224), increases in the positive direction when the output voltage setting is in the range of Vd to Vc. The increase peaks when the output voltage setting is in the range of Vc to Vb, starts decreasing when the output voltage setting is in the range of Vb to Va, and returns to zero when the output voltage setting is in the range of Va to VSS.
Referring to part (2) of FIG. 12, an increase in the positive direction in the characteristic (characteristic curve Isn_ref) of the output current difference between the nodes N201 and N202 (I (N201)−I (N202)) in the differential input section 210 affects the output voltage error characteristic (characteristic curve Ve_ref) shown in part (5) of FIG. 12. This is easily known by observing the reactions of the n-channel differential pairs (221,222) and (223, 224) taking place when the input voltages Vin1 and Vin2 for the differential input section 210 change to be higher in potential than the output voltage Vout. When the input voltages Vin1 and Vin2 change to be higher in potential than the output voltage Vout, the currents I (221) and I (223) in the n-channel differential pairs (221, 222) and (223, 224) increase, and the currents I (222) and I (224) decrease. Namely, the output current I (N201) increases and the output current I (N202) decreases. This causes the output amplification section 211 to change the output voltage Vout toward a higher potential. Referring to part (2) of FIG. 12, when the output voltage setting is in the range of voltage Vd to Va, the output current difference (I (N201)−I (N202)) increases in the positive direction. Hence, referring to part (5) of FIG. 12, as the output current difference (I (N201)−I (N202)) increases in the positive direction, the output voltage Vout is affected to change toward a higher potential resulting in generating an output voltage error toward a higher potential (in the positive direction).
In FIG. 12, part (3) represents the current characteristics of transistors 225 to 228 included in the p-channel differential pairs (225, 226) and (227, 228). In part (3) of FIG. 12, the currents I (227) and I (228) are represented by solid lines, and the currents I (225) and I (226) are represented by broken lines. The respective currents represent the drain-to-source currents in absolute value of the corresponding transistors. When the output voltage setting is in a range on the low potential supply voltage VSS side, the currents I (225) and I (228) are kept at Ip1 and the currents I (226) and I (227) are kept at Ip2. In this state, interpolation is performed normally. When, with the output voltage setting being in a range on the high potential supply voltage VDD side, the input voltages Vin1 and Vin2 rise causing the output voltage setting to rise to voltage Ve, first the common source terminal of the p-channel differential pair (225, 226) provided with the high potential input voltage Vin1 reaches the supply voltage VDD. When the output voltage setting further rises, with the common source terminal voltage of the p-channel differential pair (225, 226) being unable to rise above the supply voltage VDD, only the input voltage for the differential pair (225, 226) rises (i.e. gate-source voltages of the transistors 225 and 226 lower in absolute value). Subsequently, as the output voltage setting rises above Ve, the currents I (225) and I (226) start decreasing. When the output voltage setting rises to voltage Vg, the currents I (225) and I (226) become almost zero causing the p-channel differential pair (225, 226) to stop. In the p-channel differential pair (227, 228) provided with the input voltage Vin2, on the other hand, the common source terminal voltage reaches the high potential supply voltage VDD when the output voltage setting rises to voltage Vf. When the output voltage setting further rises, the gate-source voltages of the transistors 227 and 228 included in the p-channel differential pair (227, 228) decrease in absolute value. Subsequently, as the output voltage setting rises above Vf, the currents I (227) and I (228) start decreasing. When the output voltage setting rises to Vh, the currents I (227) and I (228) become almost zero causing the p-channel differential pair (227, 228) to stop.
In FIG. 12, part (4) represents the characteristic (characteristic curve Isp_ref) of the output current difference between the nodes N203 and N204 (I (N203)−I (N204)) of the differential input section 210. The output current I (N203) is the sum of the currents I (225) and I (227) of the p-channel differential pairs, and the output current I (N204) is the sum of the currents I (226) and I (228) of the p-channel differential pairs. The output currents I (N203) and I (N204) are coupled to the currents at the output side node and input side node, respectively, of the current mirror 280 in the output amplification section 211. According to steady-state characteristics with interpolation being performed normally, the output current difference (I (N203)−I (N204)) is normally zero. In part (4) of FIG. 12, whereas the output current difference (I (N203)−I (N204)) is zero when the output voltage setting is in a range near the low potential supply voltage VSS, the output current difference increases in the positive direction when the output voltage setting is in the range of Ve to Vh to be near the high potential supply voltage VDD. The increase in the output current difference (I (N203)−I (N204)) depends on current changes in the p-channel differential pairs. Namely, the output current difference (I (N203)−I (N204)), depending on changes in the currents I (225), I (226), I (227) and I (228) shown in part (3) of FIG. 12, increases in the positive direction when the output voltage setting is in the range of Ve to Vf. The increase peaks when the output voltage setting is in the range of Vf to Vg, starts decreasing when the output voltage setting is in the range of Vg to Vh, and returns to zero when the output voltage setting is in the range of Vh to VDD.
Referring to part (4) of FIG. 12, the characteristic (characteristic curve Isp_ref) of the output current difference between the nodes N203 and N204 (I (N203)−I (N204)) in the differential input section 210 affects the output voltage error characteristic (characteristic curve Ve_ref) shown in part (5) of FIG. 12. This is easily known by observing the reactions of the p-channel differential pairs (225,226) and (227, 228) taking place when the input voltages Vin1 and Vin2 for the differential input section 210 change to be lower in potential than the output voltage Vout. When the input voltages Vin1 and Vin2 change to be lower in potential than the output voltage Vout, the currents I (225) and I (227) in the p-channel differential pairs (225, 226) and (227, 228) increase, and the currents I (226) and I (228) decrease. Namely, the output current difference I (N203) increases and the output current difference I (N204) decreases. This causes the output amplification section 211 to change the output voltage Vout toward a lower potential. Referring to part (4) of FIG. 12, when the output voltage setting is in the range of voltage Ve to Vh, the output current difference (I (N203)−I (N204)) increases in the positive direction. Hence, referring to part (5) of FIG. 12, as the output current difference (I (N203)−I (N204)) increases in the positive direction, the output voltage Vout is affected to change toward a lower potential resulting in generating an output voltage error toward a lower potential (in the negative direction).
The mechanism in which the output voltage error increases in the output amplifier 188 shown in FIG. 10 has been described. As described, when the output voltage setting of the output amplifier 188 shown in FIG. 10 is in a range near a supply voltage, an output voltage error occurs corresponding to increases, based on steady-state characteristics, in the output current difference (I (N201)−I (N202)) on the n-channel differential pair side and in the output current difference (I (N203)−I (N204)) on the p-channel differential pair side. The steady-state characteristic of the output voltage Vout error shown in part (5) of FIG. 12 coincides with the steady-state characteristic of the output voltage error shown in FIG. 11.
In Japanese Patent Laid-Open No. 2006-050296, a technique to suppress the increase in output voltage error is disclosed. FIG. 13 shows a block diagram of an output amplifier 300 disclosed in Japanese Patent Laid-Open No. 2006-050296. The output amplifier 300 shown in FIG. 13 includes an interpolating amplifier 301, a determination section 302, and a differential pair control section 303. The determination section 302 determines whether a target signal, for example, output voltage Vout comes in a voltage range where the output voltage error of the interpolating amplifier increases and outputs a determination signal. The differential pair control section 303 stops differential pair operation when a determination signal indicating that the output voltage Vout is in a voltage range where the output voltage error of the interpolating amplifier increases is received. To be concrete, as shown in FIG. 14, the differential pair control section 303 stops the current sources for driving differential pairs. For example, when the output voltage is in a voltage range which is near a low potential supply voltage and in which the output voltage error increases, the differential pair control section 303 deactivates (stops) the current sources 331 and 332 for driving the two n-channel differential pairs. Also, when the output voltage is in a voltage range which is near a high potential supply voltage and in which the output voltage error increases, the differential pair control section 303 deactivates (stops) the current sources 333 and 334 for driving the two p-channel differential pairs. In this way, when the output voltage is in a range near a supply voltage where the output voltage error increases, the n-channel or p-channel differential pairs are stopped, so that the output voltage error is prevented from increasing.